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A Camera Payload and Processing Unit for Onboard Solar Panel Deployment Verification Using Segmentation and Contour-Based Compression

Mr Mohamed Nadhem Mraihi — FPGA Designer
Engineering Minds Munich GmbH
Engineering Payload Engineering Systems Engineering & Integration

Schedule

Poster Tuesday, May 26, 2026 · 4:30 PM · Posters Area – Kiosk 4

Abstract

The CPPU is a compact Camera Payload and Processing Unit (CPPU) for autonomous in-orbit verification of deployable mechanisms, with a focus on solar panel deployment status and subsequent anomaly monitoring. The goal is to demonstrate that decision-relevant onboard vision can replace “image-as-telemetry” by converting camera frames into reliable descriptors that support autonomous assessment while reducing downlink volume.
The CPPU interfaces cameras via MIPI-CSI-2 and enables remote sensor placement (up to ~1 m) using a flexible PCB for integration in constrained spacecraft layouts. Processing is performed on EMM’s power-efficient FPGA-SoC Smart Processing Module (SPM) using a two-stage vision pipeline: (1) a CNN-based semantic segmentation model produces pixel-wise masks separating deployable structures from background under non-ideal illumination and partial occlusions; (2) deterministic post-processing kernels—mask refinement, connected-component analysis, contour tracing, and polygon/feature reduction—compress the segmentation into sparse geometric descriptors. To accelerate segmentation and selected kernels under embedded constraints, we evaluate a soft-GPU compute approach: in the current engineering setup the soft-GPU runs on a separate accelerator board, with an architecture designed for later integration as an IP block within the SPM.
Expected outcomes include (i) substantial downlink reduction by transmitting descriptors and deployment-state estimates instead of full frames, (ii) deterministic real-time operation suitable for onboard use, and (iii) an experimentally validated processing chain addressing key smallsat challenges such as memory bandwidth, data movement from capture to compute, model quantization/portability, and verification of decision-relevant compression. The paper will describe the CPPU hardware and EGSE validation, detail the segmentation-to-descriptor pipeline, present preliminary performance results, and discuss candidate decision strategies and confidence-driven autonomy for selective downlink.

Authors

  • Mr Mohamed Nadhem Mraihi — FPGA Designer
    Engineering Minds Munich GmbH
  • Mr Sebastian Stang — Application Engineer
    Engineering Minds Munich GmbH
  • Mr Chedi Fassi — System Engineer
    Engineering Minds Munich GmbH